
Configuration MC13xx Users Manual Rev. 1.08
6.9 Firmware
6.9.1 Update Firmware
MC13xx’s logic is integrated into a FPGA (Field Programmable Gate Array), which’s configuration is
stored in an EEPROM. Upon power up or a command the FPGA is loaded with this configuration. Con-
figuration data can be downloaded via the serial interface of Camera Link®. Mikrotron may provide
configuration files (*.ibf) on request.
After download of configuration data, this data is permanently stored in EEPROM and the FPGA is
configured with the new data. Besides a power cycle, the :c command can be used to reconfigure the
FPGA with the internally stored configuration data.
*
Download of *.ibf file via serial link with 9600Bd
takes app. 1.5 min. There should be no loss of power
or communication during this time!
6.9.2 Reset and configuration of the internal FPGA
The command :c executes a reset in the camera. The FPGA will be reconfigured and all internal regis-
ters reloaded with the last saved PowerUpProfile. The FPGA is also configured after each power up.
Command: :c
Response: none
6.10 Horizontal pixelbinning
Pixelbinning adds the gray values of two adjacent pixels and outputs it as one pixel with double sensi-
tivity. In X-direction only 512 pixels are needed to cover the sensors full size. To retain aspect ratio,
every second line is omitted or vertical pixelbinning
can be activated.
Command: :r7010
Response: none
When selecting lines with r
1,
or r
3
the contents of r1 is doubled in camera logic. To address a specific
line on the sensor, the value of r1 has to be divided by two and r3 must not exceed 1ffh.
Example:
To output 256 lines from line 128, set r1 = 63 and r3 = 255 (=0xff).
6.11 Vertical pixelbinning
Vertical pixelbinning adds the gray values of two superimposed pixel of a column. This doubles sensi-
tivity and vertical field of view. To retain aspect ratio, in addition horizontal binning
must be activated.
To activate, set bit 2 in register 6.
Command example: :r6034
Response: none
22
Kommentare zu diesen Handbüchern